1. Field of the invention
The present invention relates to an image processing apparatus for use in, for example, an electronic still camera including a serial I/O type image memory.
2. Description of the Related art
Recently, electronic still cameras using a multiplicity of semiconductor memories have attracted public attention since large-capacity semiconductor memories have become available. In an electronic still camera, a switch-Y signal (a switch brightness signal) obtained by switching, for example, the RGB output of the imaging device is temporarily supplied to an FIFO (First-In First-Out) memory. A 1H delay signal and a 2H delay signal are formed by two 1H line memories by using the output from the above-described FIFO memory. The output from the FIFO memory, the 1H delay signal and the 2H delay signal are supplied to a vertical finite impulse response type filter (a vertical FIR type filter) so as to be subjected to a vertical aperture compensation. As a result, the brightness signal can be obtained.
Also, a processing is conducted in which R, G and B signals are fetched from the 1H delay signal, the thus fetched R, G and B signals are subjected to a horizontal FIR filter processing and converted into color difference signals R-Y and B-Y so that the color difference signals R-Y and B-Y are made line sequential.
The brightness signal and the line sequential color difference signal thus obtained are clamped and subjected to a blanking processing. Then, a combined synchronizing signal is added to the brightness signal so that an image is magnetically recorded on a video floppy disk by a know magnetic recording/reproducing apparatus.
However, according to the above-described conventional apparatus, two 1H line memories must be provided in addition to the FIFO memory of a predetermined capacity. It leads to a problem in that the size of the circuit in the apparatus is excessively enlarged and the manufacturing cost is thereby increased.
Furthermore, image memory devices for storing image data, in particular, storing TV image data have been widely used recently since the large capacity semiconductor device have become available. In a case where a TV image data is stored, the necessity of applying the full address to the I/O of the image memory device can be eliminated, but the address value successively changing from a predetermined value must be automatically generated. That is, the FIFO memory is used. If the FIFO memory is employed as the image memory device, the memory control can be easily implemented. Therefore, an advantage can be obtained in that the necessary number of control signal lines can be reduced and the circuit can thereby be cheaply manufactured.
However, a problem arises, when only desired data is fetched in the case where a considerably complicated processing of signals is conducted, the desired data cannot be quickly fetched. For example, in the case of a still image transmitting device such as the visual telephone, processing in which data transmission is performed with omitting predetermined pixels or processing of again transmitting data which has not been received satisfactorily cannot be quickly completed if the FIFO memory is used. In order to quickly complete the above-described processings, the circuit becomes excessively complicated.